FIFO (First In, First Out) has been well known as a method of controlling a RAM (Random Access Memory). The following describes the FIFO access control for RAM. FIG. 8 schematically illustrates the FIFO access control.
As illustrated in FIG. 8, according to the FIFO access control, initially, a first to a tenth data items are written in that order to addresses 0 to 9 of the RAM. Then, before the written data items are overwritten, the first to tenth data items are read. After that, the first to tenth data items are written in that order.
The following describes access timing of the FIFO access control. FIG. 9 illustrates control timings for a conventional RAM. Incidentally, the intervals at which data is written to one address are 20 clocks in FIG. 9. Moreover, it takes one clock to read data from each address; data is successively read out.
As illustrated in FIG. 9, each time “write enable” is input to the RAM at intervals of 20 clocks, a write pointer sequentially points at addresses 0 to 9 of the RAM and 10 data items are written to addresses 0 to 9. During the operation, it takes 20 clocks to write one data item, meaning that it takes 200 clocks to write data items to addresses 0 to 9. Moreover, the reading of the written data items is performed locally after a data item is written to the last address 9 of the RAM. During the operation, it takes one clock to read out one data item, meaning that it takes 10 clocks to read out data items from addresses 0 to 9. Incidentally, a read pointer points to the top address from which data is read. Therefore, when “read enable” is not input to the RAM, the read pointer remains at address 0.
However, the problem is that according to the above way of FIFO access control, the period during which data may be read, or readable period, is short. After pointing at the last address 9, the write pointer points at the first address 0. Then, data is overwritten. Accordingly, data needs to be read after data is written to the last address 9 and before data is written to the first address 0.
To address the problem that the readable period is short, another way of access control is well known: parts of RAM's addresses are used as redundant blocks. FIG. 10 is a diagram schematically illustrating access control with parts of RAM's addresses used as redundant blocks. Incidentally, in FIG. 10, there are two more addresses compared with the RAM illustrated in FIG. 8. However, suppose that 10 data items are written to the RAM. FIG. 11 illustrates access control timings when parts of RAM's addresses are used as redundant blocks.
As illustrated in FIG. 10, according to the access control with redundant blocks used, first, 10 data items are sequentially written to addresses 0 to 9 among 12 addresses. Then, the written 10 data items are read. After that, 10 data items are sequentially written to addresses 10, 11 and 0 to 7. That is, blocks of two addresses following the address to which the tenth data item has been written are left as redundant blocks in any case. In this manner, redundant blocks are set for data to be read or written, thereby extending the period from when the tenth data item is written until the next data item overwrites the first data item. More specifically, as illustrated in FIG. 11, the readable period is extended by an amount equivalent to the number of addresses made redundant, compared with the above way of access control.
The following describes a configuration related to the access control with redundant blocks used. FIG. 12 illustrates a control configuration for a RAM where parts of addresses are used as redundant blocks.
As illustrated in FIG. 12, provided to control the RAM are a write enable generation section, a write address generation section, a read enable generation section, and a read address generation section. In the RAM, as described above, storage areas 0 to 11 are provided, each storage area having a capacity of 10 bits. Moreover, provided around the RAM are a 10-bit flip-flop that temporarily holds write data; and a 10-bit flip-flop that temporarily holds read data.
The write enable generation section generates a 1-bit “write enable” for the RAM. Between the write enable generation section and the RAM, a 1-bit flip-flop is provided to temporarily hold the “write enable.” The write address generation section generates, as a write pointer for the RAM, a 4-bit write address. Between the write address generation section and the RAM, a 4-bit flip-flop is provided to temporarily hold the write address. The read enable generation section generates a 1-bit “read enable” for the RAM. Between the read enable generation section and the RAM, a 1-bit flip-flop is provided to temporarily hold the “read enable.” The read address generation section generates, as a read pointer for the RAM, a 4-bit read address. Between the read address generation section and the RAM, a 4-bit flip-flop is provided to temporarily hold the read address.
The following describes the operation of the read address generation section. FIG. 13 illustrates the operation of a conventional read address generation section.
As illustrated in FIG. 13, first, the read address generation section makes a determination as to whether “pre read enable,” which is “read enable” that is generated by the read enable generation section and has yet to be input into the RAM, is 1 (S901).
When the “pre read enable” is 1 (S901, YES), the read address generation section makes a determination as to whether a read address is 11 (S902).
When the read address is 11 (S902, YES), the read address generation section assigns 0 to “read address next,” which is a read address that has yet to be held by a flip-flop (S903).
On the other hand, when the read address is not 11 (S902, NO), the read address generation section assigns a value obtained by adding one and the read address to the “read address next” (S904).
In that manner, according to the conventional control method by which parts of RAM's addresses are used as redundant blocks, the “read address next” is counted up every time data is read out.    [Patent Document 1] Japanese Laid-open Patent Publication No. 2002-278831    [Patent Document 2] Japanese Laid-open Patent Publication No. 2003-288268
However, according to the above way of access control that uses redundant blocks, since the “read address next” is changed each time data is read, there is no correlation between the RAM's addresses and the order of data items to be written. Therefore, the flip-flop that temporarily holds the read address needs to continuously hold the read address. Thus the problem is that the flip-flop may not be used as a flip-flop that holds the other operations' values.